Design of a Phase Locked Loop by using 50nm CMOS Technology

All praises for the Almighty Allah, the Most Beneficial the Most Merciful. The authors wish to express their indebtedness sincere appreciation and deep sense of gratitude to the supervisor, Dr. Pran Kanai Saha, Professor, Department of Electrical and Electronic Engineering, BUET, Dhaka, for his con...

Täydet tiedot

Bibliografiset tiedot

Päätekijät:	Yeahia Been Sayeed, Sk., Shadakat Hossain, Md., Isa Mahmood, Azfar
Aineistotyyppi:	Other
Kieli:	englanti
Julkaistu:	2015
Aiheet:	Phase Locked Loop, CMOS Technology
Linkit:	http://hdl.handle.net/123456789/238
Tagit:	Lisää tagi Ei tageja, Lisää ensimmäinen tagi!