Design of a Phase Locked Loop by using 50nm CMOS Technology

All praises for the Almighty Allah, the Most Beneficial the Most Merciful. The authors wish to express their indebtedness sincere appreciation and deep sense of gratitude to the supervisor, Dr. Pran Kanai Saha, Professor, Department of Electrical and Electronic Engineering, BUET, Dhaka, for his con...

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Bibliographische Detailangaben

Hauptverfasser:	Yeahia Been Sayeed, Sk., Shadakat Hossain, Md., Isa Mahmood, Azfar
Format:	Other
Sprache:	Englisch
Veröffentlicht:	2015
Schlagworte:	Phase Locked Loop, CMOS Technology
Online-Zugang:	http://hdl.handle.net/123456789/238
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