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Design of a Phase Locked Loop by using 50nm CMOS Technology

All praises for the Almighty Allah, the Most Beneficial the Most Merciful. The authors wish to express their indebtedness sincere appreciation and deep sense of gratitude to the supervisor, Dr. Pran Kanai Saha, Professor, Department of Electrical and Electronic Engineering, BUET, Dhaka, for his con...

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Autors principals: Yeahia Been Sayeed, Sk., Shadakat Hossain, Md., Isa Mahmood, Azfar
Format: Other
Idioma:anglès
Publicat: 2015
Matèries:
Phase Locked Loop, CMOS Technology
Accés en línia:http://hdl.handle.net/123456789/238
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Sumari:All praises for the Almighty Allah, the Most Beneficial the Most Merciful. The authors wish to express their indebtedness sincere appreciation and deep sense of gratitude to the supervisor, Dr. Pran Kanai Saha, Professor, Department of Electrical and Electronic Engineering, BUET, Dhaka, for his constant guidance, valuable suggestion, constant encouragement and target toward perfection all along the course of this thesis work. The authors would like to extend their regards to them who directly and indirectly helped them in thesis work.

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