Design of a Phase Locked Loop by using 50nm CMOS Technology

All praises for the Almighty Allah, the Most Beneficial the Most Merciful. The authors wish to express their indebtedness sincere appreciation and deep sense of gratitude to the supervisor, Dr. Pran Kanai Saha, Professor, Department of Electrical and Electronic Engineering, BUET, Dhaka, for his con...

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Manylion Llyfryddiaeth

Prif Awduron:	Yeahia Been Sayeed, Sk., Shadakat Hossain, Md., Isa Mahmood, Azfar
Fformat:	Other
Iaith:	Saesneg
Cyhoeddwyd:	2015
Pynciau:	Phase Locked Loop, CMOS Technology
Mynediad Ar-lein:	http://hdl.handle.net/123456789/238
Tagiau:	Ychwanegu Tag Dim Tagiau, Byddwch y cyntaf i dagio'r cofnod hwn!