Design of a Phase Locked Loop by using 50nm CMOS Technology
All praises for the Almighty Allah, the Most Beneficial the Most Merciful. The authors wish to express their indebtedness sincere appreciation and deep sense of gratitude to the supervisor, Dr. Pran Kanai Saha, Professor, Department of Electrical and Electronic Engineering, BUET, Dhaka, for his con...
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| Formato: | Other |
| Lenguaje: | inglés |
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2015
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| Acceso en línea: | http://hdl.handle.net/123456789/238 |
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| _version_ | 1868227017270362112 |
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| author | Yeahia Been Sayeed, Sk. Shadakat Hossain, Md. Isa Mahmood, Azfar |
| author_browse | Isa Mahmood, Azfar Shadakat Hossain, Md. Yeahia Been Sayeed, Sk. |
| author_facet | Yeahia Been Sayeed, Sk. Shadakat Hossain, Md. Isa Mahmood, Azfar |
| author_sort | Yeahia Been Sayeed, Sk. |
| collection | DSpace |
| description | All praises for the Almighty Allah, the Most Beneficial the Most Merciful.
The authors wish to express their indebtedness sincere appreciation and deep sense of gratitude to the supervisor, Dr. Pran Kanai Saha, Professor, Department of Electrical and Electronic Engineering, BUET, Dhaka, for his constant guidance, valuable suggestion, constant encouragement and target toward perfection all along the course of this thesis work.
The authors would like to extend their regards to them who directly and indirectly helped them in thesis work. |
| format | Other |
| id | oai:localhost:123456789-238 |
| institution | My University |
| language | English |
| publishDate | 2015 |
| publishDateRange | 2015 |
| publishDateSort | 2015 |
| record_format | dspace |
| spelling | oai:localhost:123456789-2382016-01-21T17:37:08Z Design of a Phase Locked Loop by using 50nm CMOS Technology Yeahia Been Sayeed, Sk. Shadakat Hossain, Md. Isa Mahmood, Azfar Phase Locked Loop, CMOS Technology All praises for the Almighty Allah, the Most Beneficial the Most Merciful. The authors wish to express their indebtedness sincere appreciation and deep sense of gratitude to the supervisor, Dr. Pran Kanai Saha, Professor, Department of Electrical and Electronic Engineering, BUET, Dhaka, for his constant guidance, valuable suggestion, constant encouragement and target toward perfection all along the course of this thesis work. The authors would like to extend their regards to them who directly and indirectly helped them in thesis work. Phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz. This thesis contains discrete components involving the Phase Detector and Voltage Controlled Oscillator and Filter. The Phase Detector and the Voltage Controlled Oscillator are designed with 50nm CMOS technology. The Filter is designed with microstrip transmission line. The Phase Detector, Voltage Controlled Oscillator and Band Pass Filter are designed and simulated using the softwares - LTSPICE, HSPICE, ADS. The simulated results are in good agreement. Process Scattering and Temperature variation have been applied in this thesis. Department of Electrical, Electronics and Communication Engineering (EECE) MILITARY INSTITUTE OF SCIENCE AND TECHNOLOGY (MIST) 2015-12-01T04:36:06Z 2015-12-01T04:36:06Z 2014-12 Other http://hdl.handle.net/123456789/238 en application/pdf |
| spellingShingle | Phase Locked Loop, CMOS Technology Yeahia Been Sayeed, Sk. Shadakat Hossain, Md. Isa Mahmood, Azfar Design of a Phase Locked Loop by using 50nm CMOS Technology |
| title | Design of a Phase Locked Loop by using 50nm CMOS Technology |
| title_full | Design of a Phase Locked Loop by using 50nm CMOS Technology |
| title_fullStr | Design of a Phase Locked Loop by using 50nm CMOS Technology |
| title_full_unstemmed | Design of a Phase Locked Loop by using 50nm CMOS Technology |
| title_short | Design of a Phase Locked Loop by using 50nm CMOS Technology |
| title_sort | design of a phase locked loop by using 50nm cmos technology |
| topic | Phase Locked Loop, CMOS Technology |
| url | http://hdl.handle.net/123456789/238 |
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