Design of a Phase Locked Loop by using 50nm CMOS Technology
All praises for the Almighty Allah, the Most Beneficial the Most Merciful. The authors wish to express their indebtedness sincere appreciation and deep sense of gratitude to the supervisor, Dr. Pran Kanai Saha, Professor, Department of Electrical and Electronic Engineering, BUET, Dhaka, for his con...
保存先:
| 主要な著者: | , , |
|---|---|
| フォーマット: | Other |
| 言語: | 英語 |
| 出版事項: |
2015
|
| 主題: | |
| オンライン･アクセス: | http://hdl.handle.net/123456789/238 |
| タグ: |
タグなし, このレコードへの初めてのタグを付けませんか!
|
| 要約: | All praises for the Almighty Allah, the Most Beneficial the Most Merciful.
The authors wish to express their indebtedness sincere appreciation and deep sense of gratitude to the supervisor, Dr. Pran Kanai Saha, Professor, Department of Electrical and Electronic Engineering, BUET, Dhaka, for his constant guidance, valuable suggestion, constant encouragement and target toward perfection all along the course of this thesis work.
The authors would like to extend their regards to them who directly and indirectly helped them in thesis work. |
|---|