APA (7 वां संस्करण) प्रशस्ति पत्र
Shahrin, M., Tabassum, Z., & Lim, A. I. (2019). Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology. DEPARTMENT OF ELECTRICAL, ELECTRONIC AND COMMUNICATION ENGINEERING.
शिकागो शैली (17वां संस्करण) प्रशस्ति पत्र
Shahrin, Meem, Zarin Tabassum, और Aniqa Ibnat Lim. Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 Nm CMOS Process Technology. DEPARTMENT OF ELECTRICAL, ELECTRONIC AND COMMUNICATION ENGINEERING, 2019.
एमएलए (9वां संस्करण) प्रशस्ति पत्र
Shahrin, Meem, et al. Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 Nm CMOS Process Technology. DEPARTMENT OF ELECTRICAL, ELECTRONIC AND COMMUNICATION ENGINEERING, 2019.
चेतावनी: ये उद्धरण हमेशा 100% सटीक नहीं हो सकते हैं.