APA-viite (7. p.)
Shahrin, M., Tabassum, Z., & Lim, A. I. (2019). Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology. DEPARTMENT OF ELECTRICAL, ELECTRONIC AND COMMUNICATION ENGINEERING.
Chicago-viite (17. p.)
Shahrin, Meem, Zarin Tabassum, ja Aniqa Ibnat Lim. Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 Nm CMOS Process Technology. DEPARTMENT OF ELECTRICAL, ELECTRONIC AND COMMUNICATION ENGINEERING, 2019.
MLA-viite (9. p.)
Shahrin, Meem, et al. Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 Nm CMOS Process Technology. DEPARTMENT OF ELECTRICAL, ELECTRONIC AND COMMUNICATION ENGINEERING, 2019.
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