Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology
First and foremost we would like to give our heartfelt gratitude to our parents who have been a constant pillar of support for us throughout university. This would not be possible without their encouragement and motivation. To Md. Tawfiq Amin, PhD, EME, Instructor Class B, Department of Electrica...
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DEPARTMENT OF ELECTRICAL, ELECTRONIC AND COMMUNICATION ENGINEERING
2019
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| Online Access: | http://hdl.handle.net/123456789/433 |
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| author | Shahrin, Meem Tabassum, Zarin Lim, Aniqa Ibnat |
| author_browse | Lim, Aniqa Ibnat Shahrin, Meem Tabassum, Zarin |
| author_facet | Shahrin, Meem Tabassum, Zarin Lim, Aniqa Ibnat |
| author_sort | Shahrin, Meem |
| collection | DSpace |
| description | First and foremost we would like to give our heartfelt gratitude to our parents who have
been a constant pillar of support for us throughout university. This would not be
possible without their encouragement and motivation.
To Md. Tawfiq Amin, PhD, EME, Instructor Class B, Department of Electrical,
Electronic and Communication Engineering (EECE), Military Institute of Science and
Technology (MIST), for his supervision in our understanding of beneficial advice in the
digital design and designing of various adders, helping us in performance analysis, the
proof readings of our rough drafts as well as for helping us in our academics. We would
not have been able to do this without his effort.
We would like to extend our regards to them who directly and indirectly helped us
during this journey. |
| format | Thesis |
| id | oai:localhost:123456789-433 |
| institution | My University |
| language | English |
| publishDate | 2019 |
| publishDateRange | 2019 |
| publishDateSort | 2019 |
| publisher | DEPARTMENT OF ELECTRICAL, ELECTRONIC AND COMMUNICATION ENGINEERING |
| publisherStr | DEPARTMENT OF ELECTRICAL, ELECTRONIC AND COMMUNICATION ENGINEERING |
| record_format | dspace |
| spelling | oai:localhost:123456789-4332019-03-13T04:39:27Z Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology Shahrin, Meem Tabassum, Zarin Lim, Aniqa Ibnat First and foremost we would like to give our heartfelt gratitude to our parents who have been a constant pillar of support for us throughout university. This would not be possible without their encouragement and motivation. To Md. Tawfiq Amin, PhD, EME, Instructor Class B, Department of Electrical, Electronic and Communication Engineering (EECE), Military Institute of Science and Technology (MIST), for his supervision in our understanding of beneficial advice in the digital design and designing of various adders, helping us in performance analysis, the proof readings of our rough drafts as well as for helping us in our academics. We would not have been able to do this without his effort. We would like to extend our regards to them who directly and indirectly helped us during this journey. This thesis paper comprises the study and performance analysis of four full adders with various topologies. Propagation delay, power dissipation and power delay product are the parameters to measure the performance of full adders. The overall performance can be improved by reducing power and delay which is done by optimizing the transistor size. For meeting the demands of tech-savvy fast progressing world of electronics, the sole focus for adder architecture is on making it more efficient. The design and simulation is carried out for four full adders (Conventional, transmission gate, 14T & GDI based technique) for transistor count, power dissipation, delay and power delay products. It is performed in virtuoso platform, using Cadence tool with available GPDK –90nm kit having MOS Capacitance value of 50 femto farad. The width of NMOS and PMOS is 120nm and 240nm respectively. Delay estimation is obtained by taking the average propagation delay. Transmission gate full adder has sheer advantage of high speed but consumes more power. On the other hand, GDI full adder gives reduced voltage swing not being able to pass logic 1 and logic 0 completely showing degraded output. Transmission gate full adder shows better performance in terms of delay, whereas 14T full adder shows better performance considering overall factors. 2019-03-13T04:39:27Z 2019-03-13T04:39:27Z 2017-12 Thesis http://hdl.handle.net/123456789/433 en application/pdf DEPARTMENT OF ELECTRICAL, ELECTRONIC AND COMMUNICATION ENGINEERING |
| spellingShingle | Shahrin, Meem Tabassum, Zarin Lim, Aniqa Ibnat Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology |
| title | Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology |
| title_full | Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology |
| title_fullStr | Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology |
| title_full_unstemmed | Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology |
| title_short | Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology |
| title_sort | comparative analysis of different cmos full adder using cadence in 90 nm cmos process technology |
| url | http://hdl.handle.net/123456789/433 |
| work_keys_str_mv | AT shahrinmeem comparativeanalysisofdifferentcmosfulladderusingcadencein90nmcmosprocesstechnology AT tabassumzarin comparativeanalysisofdifferentcmosfulladderusingcadencein90nmcmosprocesstechnology AT limaniqaibnat comparativeanalysisofdifferentcmosfulladderusingcadencein90nmcmosprocesstechnology |