DESIGN OF A PHASE LOCKED LOOP USING 50NM CMOS TECHNOLOGY / SK. Yeahia Been Sayed, Md. Shadat Hossain, Azfar Isa Mahmood.
Guardado en:
| Autor Corporativo: | |
|---|---|
| Otros Autores: | , |
| Formato: | Libro |
| Lenguaje: | inglés |
| Publicado: |
Dhaka :
EECE DEPT MIST ,
c 2014 .
|
| Materias: | |
| Etiquetas: |
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Ejemplares similares: DESIGN OF A PHASE LOCKED LOOP USING 50NM CMOS TECHNOLOGY /
- Design of a Phase Locked Loop by using 50nm CMOS Technology
- TRACKING OF GRID VOLTAGE ENVELOPE AND FLICKER USING PHASE LOCKED LOOP AND KALMAN FILTER TECHNIQUE /
- DESIGN AND ANALYSIS OF AN AREA EFFICIENT, LOW POWER WIDE RANGE PHASE LOCKED LOOP FOR WIRELESS COMMUNICATION APPLICATIONS /
- Tracking of grid voltage envelope and flicker using phase locked loop and Kalman filter technique
- DESIGN AND ANALYSIS OF A 5GB/S HALF-RATE CLOCK AND DATA RECOVERY CIRCUIT IN 90 NM CMOS TECHNOLOGY /
- Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology