Eitemau Tebyg: DESIGN OF A PHASE LOCKED LOOP USING 50NM CMOS TECHNOLOGY /
- Design of a Phase Locked Loop by using 50nm CMOS Technology
- Tracking of grid voltage envelope and flicker using phase locked loop and Kalman filter technique
- TRACKING OF GRID VOLTAGE ENVELOPE AND FLICKER USING PHASE LOCKED LOOP AND KALMAN FILTER TECHNIQUE /
- Comparative Analysis of Different CMOS Full Adder Using Cadence in 90 nm CMOS Process Technology
- DESIGN AND ANALYSIS OF AN AREA EFFICIENT, LOW POWER WIDE RANGE PHASE LOCKED LOOP FOR WIRELESS COMMUNICATION APPLICATIONS /
- DESIGN AND ANALYSIS OF LOW NOISE LOW POWER FREQUENCY SYNTHESIZERS FOR WIRELESS COMMUNICATIONS USING 90 NM CMOS TECHNOLOGY
Pwnc: Thesis Paper of EECE in B.Sc Prog.
- DESIGN AND CHARACTERIZATION OF BULK AND SOL FINFETS /
- BASE TRANSIT OF A GRADED BANE ALyGa1-yAs HBT USING THE ANALYTICAL MODEL DEVELOPED FOR SIGE DEVICE WITH FOR GAUSSIAN DOPED BASE /
- THE EARLY VOLTAGE AND CURRENT GAIN OF IN GA AS DOUBLE HETERO JUNCTION BIPOLAR TRANSISTOR /
- IMPROVEMENT OF EXISTING SOLAR HOME SYSTEM IN MIST ADMINISTRATION BUILDING USING PV YST & RET SCREEN SOFTWARE /
- FAULT DIAGNOSIS OF DIFFERENTIAL AMPLIFIER ANALOG CIRCUITS USING BJT (ITC 97 BENCHMARK CIRCUITS) UTILIZING COMBINED EFFECT OF GAIN AND PHASE OF OUTPUT VOLTAGE WITH FREQUENCY /
- MODELING AND SIMULATION FOR EFFICIENCY OF III-V CONCENTRATOR PHOTOVOLTAICS /
Pwnc: Electrical, Electronic and Communication Engineering.
- INTERPOLATION BASED ADAPTIVE REVERSIBLE DATA HIDING FOR DIGITAL IMAGE APPLICATIONS /
- ENERGY EFFICIENT OPERATIONS OF COMP BASED LTE-A CELLULAR NETWORKS WITH HYBERID POWER SUPPLIES /
- DESIGN AND CHARACTERIZATION OF BULK AND SOL FINFETS /
- BASE TRANSIT OF A GRADED BANE ALyGa1-yAs HBT USING THE ANALYTICAL MODEL DEVELOPED FOR SIGE DEVICE WITH FOR GAUSSIAN DOPED BASE /
- THE EARLY VOLTAGE AND CURRENT GAIN OF IN GA AS DOUBLE HETERO JUNCTION BIPOLAR TRANSISTOR /
- EFFECT OF POLARIZATION MODE DISPERSION (PMD) IN DIFFERENT CORE SHAPES AND BIT ERROR RATE (BER) PERFORMANCE IN FIBER OPTIC COMMUNICATION /